SBIR-STTR Award

The feasibility of a multiprocessor architecture for real-time OR near-real-time synthetic aperature radar (SAR) digital image formation and postprocessing will be studied. The proposed architecture will use state-of-the-art digital signal processors as processing elements. Near-neighbor mesh and barrel shifter (pm2i) network interconnect topologies will be studied in terms of throughput versus complexity tradeoffs. Issues involving memory storage organization and access for large image retrieval and segmentation will be investigated. In addition, image reduction versus computer requirement assessments will be made against the candidate architecture.