SBIR-STTR Award

MMIC yield is the significant factor in determining both chip cost and level of integration. In order to maximize yield, it is necessary to establish a consistent, reproducible process control, coupled with creative circuit design techniques used to create ship sets which are tolerant to process variations. A large proportion of the final cost for the end product is related to the assembly and final testing. This exploratory study will conduct cost analysis research on computer assisted techniques that will have a direct impact on the yields and hence, costs at various monitor points during the manufacture, assembly and testing of MMIC's. An x-band phase array radar chip set will be utilized as a test vehicle for this study. Direct cost and yield comparisons will be conducted against an equivalent antic fabrication.

To obtain an accurate cost and yield figures for a monolithic subsystem it becomes necessary to link the design, processing and fabrication, testing and assembly activities to a common monitoring activity. Such an activity would direct towards obtaining data from process, fabrication and testing and make substantial use of in process testing to screen out circuits at an early stage. MMIC yield is the significant factor in determining both chip cost and level of integration. In order to maximize yield it is necessary to establish a consistent, reproducible process control, coupled with creative circuit design techniques used to create chip sets which are tolerant to process variation. A large proportion of the final cost is also related to final assembly and testing. The Phase II work will develop a calibrated model for cost and yield analysis and will incorporate the average component yield factors for each active and passive element, determined from the process. In addition the analysis, as a software package, will have flexibility so as to let any gallium arsenide foundry to calibrate it to their process. The final software package will be marketed commercially in Phase III.