In this project we proposed to demonstrate the feasibility of a novel analysis techniques to produce fingerprints for authentication and reliability monitoring of ICs die before DER, after DER, and while in operation. The proposed technique is based on Power Fingerprinting (PFP) technology, which is an integrity assessment approach based on analog side-channel analysis (e.g. electromagnetic emissions or power consumption) already used to detect counterfeit ICs and hardware Trojans. The ability of PFP to detect counterfeit electronic parts has been demonstrated on a number of platforms and devices. For this Phase I effort we will enhance current PFP implementation to support multiple sensors from multiple domains in order to improve counterfeit detection performance; validate the ability of PFP to detect potential damage to the die suffered during the DER process, while remaining robust to the changes in the side-channels potentially introduced by the new packaging; and evaluate the ability of PFP to leverage predictive modeling techniques to predict end of life for the test platforms.;
Benefit: The proposed project leverages over eight years of technology development, including side-channel feature extraction, analytical tools to extract baselines, detector and classifier design, and more. The final goal is to transition PFP technology into a complete deployable solution to perform agile, non-destructive inspections of electronic parts in a production environment and test labs across the Department of Defense.This project will provide a proof-of-concept tool to demonstrate the feasibility of the proposed approach. More importantly, this project will identify a scalable architecture based on COTS components and the necessary technical requirements for the different configuration to achieve the expected performance metrics providing a solid foundation for Phase II and beyond.
