SBIR-STTR Award

High Performance Computer Modeling of Electrostatic Discharge Testing
Award last edited on: 10/26/2017

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$202,852
Award Phase
1
Solicitation Topic Code
02c
Principal Investigator
Gregory Moss

Company Information

Remcom Inc

315 South Allen Street Suite 222
State College, PA 16801
   (814) 861-2543
   rjl@remcom.com
   www.remcominc.com
Location: Multiple
Congr. District: 15
County: Centre

Phase I

Contract Number: DE-SC0017164
Start Date: 2/21/2017    Completed: 2/20/2018
Phase I year
2017
Phase I Amount
$202,852
The proposed project, “High Performance Computer Modeling of Electrostatic Discharge Testing, ” addresses topic 2c of DOE Solicitation DE-FOA-0001618 requesting the development of easy-to-use, high performance computational tools for the engineering and manufacturing industries. Historically, scientists and engineers have spent many man-hours developing custom computational codes and algorithms to fit their specific modeling needs, however, many of these codes are not widely accessible to the scientific community as a whole because of their complexity and lack of user-friendly graphical user interfaces (GUIs). Additionally, recent advances in high performance computing (HPC) technologies including massively parallel processing and graphics processing unit (GPU) programming are not fully utilized due to the complexity of software development and cost of maintaining large computing clusters in house. The goal of this project is to develop a software tool capable of computationally modeling the electrostatic discharge testing process utilized by the consumer electronics and mobile device industries. The computational approach will be based on the finite-difference time-domain (FDTD) method to simulate electromagnetic field propagation resulting from the use of an ESD simulator (or gun) and the Monte Carlo method to model dielectric breakdown resulting from spark (electrostatic) discharges. Furthermore, integrating these methods with existing circuit simulation capabilities will allow users to simulate the entire ESD testing process and pinpoint specific electronic components in risk of damage. Combining these computational methods with a modern and intuitive user interface and HPC capabilities will allow users to optimize their ESD and electromagnetic compatibility (EMC) designs in an efficient manner and reduce the number of costly hardware prototypes needed during the design phase. Given the lack of commercial tools currently available capable of analyzing the entire ESD testing process, the resulting product should be extremely marketable to all industries using ESD testing.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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