The fundamental requirement for interconnect is to meet the high-speed needs of chips despite further scaling of feature sizes, while the main function of an interconnect system is to distribute clock and/or other signals among various circuit functions on a chip. As the clock has been doubling its present speed over a period of less than half a decade, current interconnects technologies have already started to face signal integrity challenges at high data rates. Interconnect time bandwidths, clock skew, excessive AC losses in PCB traces due to skin effects, via effects, impedance discontinuities and crosstalk, are a few examples of these challenges Phase I Objective Demonstrate the feasibility of design and development of a scalable, reconfigurable optical switching network for integration with the next generation Network Enabled Wavelength Division Multiplexing Highly Integrated Photonics. Analysis of potential optical networking components suitable for high data rate optical signal transmission will be studied in detail through numerical analysis and preliminary prototype demonstration will be investigated. What is to be done in Phase I In Phase I effort, Lumilant Inc. will develop a silicon-photonic compatible, bi-directionaly reconfigurable, chipscale nanophotonic switching fabric which will allow multiple pairs of ports to communicate simultaneously with data rates close to 160G bit per channel, providing a huge aggregation of bandwidth and with channel to channel extinction ratio close to -45dB. It is anticipated that the switching fabric designs developed to be orders of magnitude smaller than their convectional counterparts. Such miniaturisation will be a critical factor in attaining lower switching power, scalable optical network designs capable of supporting Terabytes of data rates. Commercial Applications Possibilities for building an optically interconnected network for advanced digital applications are significant. This work will be useful in military applications ranging from communications to missile guidance to long-range imaging. However, due to the nature of the proposed device structure and fabrication scheme this project will find interest with many existing Optical signal-processing modules for fast signal acquisition on a chip scale. The proposed research will facilitate the optical signal processing on a chip scale and eventually to an optically interconnected system/chip. The ability to integrate photonic functions into a chip to reduce overall chip size will enable the development of next generation photonic integrated circuits and will advance research in various defense areas including; physics, materials, devices and photonic integrated circuits, processing and chip architecture particularly for Intelligence, Surveillance, Reconnaissance (ISR), National Missile defense (NMD) and communication mission areas. Realization of a reconfigurable optically interconnected chip would meet the requirements for the majority of the defense programs; including all optical switching on a chip, multistage tunable wavelength converters and multiplexers, all optical pushpull converters, compact beamsteering, very fine pointing, tracking, and stabilization control; and ultra-lightweight antennas and eventually pave the path towards an optically interconnected routing chip.
Keywords: Optical Switching Fabric, Optical Network, Silicon Photonic, LOCOS, WDM Summary for Members of Congress Todays communication networks traditionally have been designed an optimized for specific applications over preengineered, well defined network paths. Unfortunately in this new digital era with every thing available on demand, the traditional approach becomes cost prohibitive. The results is todays optical networks must evolve to meet the new challenges. Lumilants proposed optical network is scalable, reconfigurable to meet current and future highdata rate demands of commercial and defense applications demanding beyond thousands of Gigabytes of data transmission and hence will provide an a a radically new interconnect architecture that minimizes the routing delay through the chip/system to enable increased performance, reduced costs, and faster time to market.
