SBIR-STTR Award

Analog Stem Cells and Flow for Automated Analog Layout
Award last edited on: 7/10/2015

Sponsored Program
SBIR
Awarding Agency
NSF
Total Award Amount
$150,000
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Choshu Ito

Company Information

Totic Technology Inc

19733 Graystone Lane
San Jose, CA 95120
   (408) 440-2254
   N/A
   www.totictech.com
Location: Single
Congr. District: 19
County: Santa Clara

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2015
Phase I Amount
$150,000
The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to transform the analog design landscape, eliminating the analog design bottleneck by creating a new way to do analog layout using digital place and route technology. The potential impact is broad and encompasses most, if not all, semiconductor companies and design houses, who will be able to gain reductions in cost and design schedule by utilizing the technology that will begin to be developed in this proposal. The clear analogy is with digital Place and Route (P and R) technology which has now almost completely replaced custom digital design and layout. Except for few very specialized niches, digital P and R is the standard tool used by everyone on nearly every chip. The company's stem cells and flow can become the equivalent of this technology for analog and mixed signal designs.

This Small Business Innovation Research (SBIR) Phase I project targets several facets of the flow to prove that analog layout productivity can be increased by orders of magnitude. A continuous time linear equalizer circuit layout will be created using our stem-cell Place and Route flow, and compared to a hand-crafted layout. By increasing the stem-cell layout active density, expanding the stem-cell library to minimize mapping errors, and creating macros hierarchically, the company will reduce layout-induced parasitics such that area, power and performance will match or exceed the handcrafted version. A layout will be generated with the company's flow to prove compatibility with analog circuits other than amplifiers or linear equalizers. Also, the project will prove portability from one foundry process to another to show that post-extraction simulated performance is maintained in the new process.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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