In Phase II Tezzaron will design a 2 layer 8Mb ReRAM (RRAM) memory device, extendable to 17 layers or 128Gb as a test chip or 1Gb as a final device. The first layer of the design is a controller layer with power control, drivers, user interface circuitry (i.e. peripheral circuitry), and sense amplifiers. The second layer of the design holds the memory cells and minimal circuitry to allow signal multiplexing of the through silicon vias (TSVs) that vertically connect the stack. This memory cell layer can be stacked serially, up to 16 memory cell layers, to yield a 17 layer device. Each memory cell layer will have 8Mb of user memory, exclusive of the built-in error detection and correction coding and the redundant memory bits. The interface will support the Honeywell x8 and x16 memory interface, the FPGA download mode interface, and a DDR2 DRAM compatible interface.
Benefit:The benefits of this program will include the availability of resistive memory for harsh environments as well as making a non-volatile ReRAM process technology add-on (split-fab) generally available to commercial entities. ReRAM technology is generally considered to be the best technology to succeed Flash memory. The higher performance and greater endurance will also alter most future computer designs by providing a new storage class memory that has SSD like density with near DRAM access speed. This will revolutionize machine architecture and reduce compute power requirements. The split-fab option will permit semiconductor foundry customers to add ReRAM non-volatile memory to their devices as a 3rd party post fabrication process not effecting the original primary foundry processes. As most leading edge foundry processes don't offer a reprogrammable non-volatile memory option, this will make possible new hardware with higher density, lower power and much improved security.
