SBIR-STTR Award

This Small Business Innovation Research Phase I project is aimed at developing a spin torque magnetoresistive random access memory (ST-MRAM) that has significantly reduced write current. The highest bit density is possible if the switching current is low enough to be passed by a minimum sized access transistor beneath each magnetic tunnel junction (MTJ) storage device. Reducing the write current also improves reliability because the smaller current density through the MTJ during the write operation reduces the stress on the thin dielectric tunnel barrier. ST-MRAM has the potential to provide non-volatility, high density, high speed, low power, and unlimited endurance in a single memory. ST-MRAM technology has the potential to meet the need for a high-performance, scalable semiconductor memory while providing benefits in power consumption that are critical in portable electronics and increasingly valued in many other areas, such as enterprise computing. Conventional semiconductor memories like Static RAM, Flash, and Dynamic RAM are facing significant scaling challenges in the coming years and none of them have the unique set of attributes provided by MRAM.

This Small Business Innovation Research (SBIR) Phase II project aims to demonstrate a high-performance spin torque magnetoresistive random access memory (ST-MRAM). ST-MRAM technology promises a powerful combination of non-volatility, high density, high speed, and low power. The major impediment to commercializing ST-MRAM has been that the write current for programming the magnetic tunnel junction (MTJ) bits are too large. Large write current can cause tunnel barrier breakdown, thereby compromising memory reliability. Additionally, large write current requires large select transistors beneath each bit, preventing high density. In Phase I project, an MTJ bit design with a low enough write current has been successfully demonstrated. In this Phase II project, a large, high-density ST-MRAM demonstration circuit will be developed using this improved bit design. Several novel circuit design approaches that have potential for higher speed, higher density and lower power will be evaluated. The circuit will provide the bit statistics needed to optimize the bit design and enhance the yield to the level required for a highly reliable commercial ST-MRAM. The broader/commercial impacts of this project will be the potential to enable the commercial applications of ST-MRAM. The Toggle MRAM is already finding many applications in the stand-alone memory market including networking, industrial controls, data server systems, military, aerospace industry etc. However, in order for MRAM to achieve its full commercial potential, higher density and lower power consumption are needed. High density translates to lower cost. Reducing power consumption is increasingly valued in areas such as portable electronics or even enterprise computing. ST-MRAM technology has the potential to meet these needs by combining non-volatility, high density, high speed, low power, unlimited endurance, and scalability in a single memory.