SBIR-STTR Award

LIT proposes developing a processor socket that detects system configuration attributes and protects the system from interposers, probing, and other dynamic reverse engineering techniques. The LIT AT Processor Socket (ATPS) would utilize circuitry between the microprocessor socket connector and the motherboard (or Circuit Card Assembly, CCA) to ensure that the system is secure. The circuitry will be designed into a unit that is incorporated into the socket or incorporated into the Circuit Card Assembly (or motherboard). The ATPS circuitry will utilize LIT Phantom Sensor technology to verify that the motherboard/CCA system is in the appropriate configuration before allowing processing. LIT will work with Pikewerks Corporation to provide a tightly coupled hardware/software solution. LIT’s Phantom Sensor technology is a revolutionary application of a basic principle. Phantom Sensors allow a system to measure its own complex impedance to determine if it has been, or is being, modified. LIT proposes developing the capabilities of LIT Phantom Sensor technology for characterizing the socket and the interface between the CCA and processor in order to determine if the system has been tampered with or altered.

Keywords:
Reverse Engineering, Anti-Tamper, Authentication, Socket, Processor, Tamper Response

LIT accomplished all Phase I goals and technical objectives. During Phase I, LIT designed a zero power/ultra low power sensor using an ultra low power microprocessor and an electromagnetic sensing element. Embedded code was developed, providing primary anti-tamper function, as well as a real time clock, event logging, and event read-back. Active and passive mode sensors were developed and demonstrated such anti-tamper capabilities as touch, probe, and volume compromise detection. In Phase II, LIT will mature this technology by developing a Wireless Attached Sensor Package (WASP) button to provide anti-tamper functions without requiring an electrical connection to existing hardware, a Transportation Sensor System (TSS) Sensor to ensure package and shipping configuration integrity during transit, and guidelines and instructions for implementing Capacitive Tamper Sensors (CTS) into new designs. The LIT anti-tamper team, including Lockheed Martin Mission Systems and Signals (LMCO MS2), will achieve TRL7 by demonstrating WASP and TSS on tactical hardware. LIT will characterize and evaluate sensor behavior by testing in different physical environments, specifically refining algorithms for event detection and noise rejection. Additional work will include evaluating size and technology impacts to sensor sensitivity and false detection performance, as well investigating power harvesting and conservation.

Keywords:
Ultra Low Power, Microprocessor, Mode Sensor, Anti-Tamper, Electromagnetic Tamper Sensors, Shipping Configuration Integrity, Event Detection, Sensor Behavior