SBIR-STTR Award

FPGAs have become one of the most popular implementation media for digital circuits on account of their low NRE costs, field programmability, and time to market advantages over ASICs. However, FPGAs' greatest strength -- reconfigurability -- is also the source of their low performance and high power consumption. GoofyFoot Labs proposes the AMP 3D-FPGA, an innovative FPGA architecture, that achieves ASIC-like performance with significantly lower power consumption than conventional FPGA architectures. The AMP 3D-FPGA achieves 1.7-GHz peak performance while simultaneously reducing standby power consumption by 70% and dynamic power consumption by nearly 50% over other 65-nm FPGAs making it suitable for high performance and mobile domains. Additionally, the AMP 3D-FPGA provides added benefit to DoD applications because its innovative architecture improves its anti-tamper properties by making it more resilient to side-channel and fault attacks. In the Phase I program, GoofyFoot Labs will develop the AMP architecture and demonstrate its power and performance improvements.

Keywords:
Fpga, High Speed, Low Power, 3-D Integration, High Performance

FPGAs are widely used in nearly every DoD electronics system because of their processing capabilities, low NRE costs, field programmability, and time to market advantages over ASICs. However, FPGAs? greatest strength ? reconfigurability ? is also the source of their low performance and high power consumption limiting functionality and battery life of mobile applications. GoofyFoot Labs has developed the AMP FPGA, a low risk architectural breakthrough that simultaneously achieves the Army?s goals of enhancing tactical radio performance, connectivity, and survivability with significantly reduced power consumption. The AMP FPGA achieves unprecedented performance operating at a maximum of 1.73 GHz. The AMP FPGA?s novel architecture does not just achieve theoretical improvements; implemented circuits operate on average 3.7x faster on the AMP FPGA than cutting edge conventional FPGAs. Without sacrificing performance, the AMP FPGA reduces static power consumption by 10x and dynamic power consumption by 25x when compared to conventional FPGAs, enabling 2.5x longer mission runtimes and reduced recharge downtime with existing battery technologies. Furthermore, the AMP FPGA is inherently robust to harsh environmental conditions. The AMP FPGA is well suited for SDR, radar, video/image processing, electronic warfare, and signals intelligence applications, and provides breakthrough capabilities for both mobile and ground-based systems.

Keywords:
Low Power, Fpga, High Performance, Software Defined Radio, Tactical Radio, Longer Mission Runtime